PXD10RM Datasheet, PDF (325/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

11.8.7 Interrupts/DMA Requests
The DSPI has five conditions that can generate interrupt requests only, and two conditions that can
generate interrupt.
Table 11-25 lists the six conditions.
Table 11-25. Interrupt and DMA Request Conditions
Condition
Flag
Interrupt
End of transfer queue has been reached (EOQ) EOQF
X
TX FIFO is not full
TFFF
X
Current frame transfer is complete
TCF
X
TX FIFO underflow has occurred
TFUF
X
RX FIFO is not empty
RFDF
X
RX FIFO overflow occurred
RFOF
X
A FIFO overrun occurred¹
TFUF ORed with RFOF
X
1 _{The FIFO overrun condition is created by ORing the TFUF and RFOF flags together.}
DMA
X
X
Each condition has a flag bit and a request enable bit. The flag bits are described in the Section 11.7.2.4,
DSPI Status Register (DSPIx_SR) and the request enable bits are described in the Section 11.7.2.5, DSPI
DMA / Interrupt Request Select and Enable Register (DSPIx_RSER). The TX FIFO fill flag (TFFF) and
RX FIFO drain flag (RFDF) generate interrupt requests or DMA requests depending on the TFFF_DIRS
and RFDF_DIRS bits in the DSPIx_RSER.
11.8.7.1 End of Queue Interrupt Request (EOQF)
The end of queue equest indicates that the end of a transmit queue is reached. The end of queue request is
generated when the EOQ bit in the executing SPI command is asserted and the EOQF_RE bit in the
DSPIx_RSER is set. Refer to the EOQ bit description in Section 11.7.2.4, DSPI Status Register
(DSPIx_SR). Refer to Figure 11-14 and Figure 11-15 that illustrate when EOQF is set.
11.8.7.2 Transmit FIFO Fill Interrupt or DMA Request (TFFF)
The transmit FIFO fill request indicates that the TX FIFO is not full. The transmit FIFO fill request is
generated when the number of entries in the TX FIFO is less than the maximum number of possible entries,
and the TFFF_RE bit in the DSPIx_RSER is set. The TFFF_DIRS bit in the DSPIx_RSER selects whether
a DMA request or an interrupt request is generated.
11.8.7.3 Transfer Complete Interrupt Request (TCF)
The transfer complete request indicates the end of the transfer of a serial frame. The transfer complete
request is generated at the end of each frame transfer when the TCF_RE bit is set in the DSPIx_RSER.
Refer to the TCF bit description in Section 11.7.2.4, DSPI Status Register (DSPIx_SR). Refer to
Figure 11-14 and Figure 11-15 that illustrate when TCF is set.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
11-43