PXD10RM Datasheet, PDF (251/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0000000000000000
W
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ALTA
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 9-17. eMIOS200 UC Alternate A Register (EMIOSALTA[n])
The EMIOSALTA[n] register provides an alternate address to access A2 channel registers in restricted
modes (GPIO) only. If EMIOSA[n] register is used along with EMIOSALTA[n], both A1 and A2 registers
can be accessed in these modes. Table 9-13 summarizes the EMIOSALTA[n] writing and reading accesses
for all operation modes.
9.5 Functional Description
The eMIOS200 provides independent channels (UC) that can be configured and accessed by a host MCU.
Up to four time bases can be shared by the channels through four counter buses and each channel can
generate its own time base. Optionally one of the counter buses can be driven by an external time base
imported through the real-time signal interface.
The eMIOS200 module is based on a multi-bus timer architecture in which several timer channels are used
to drive counter buses that are shared among the channels. There are 4 counter buses in the module: one
global counter bus, shared by all channels and 4 local counter buses, each one dedicated to a slice of 8
channels. Counter bus A is referred to as the global counter bus. Counter buses B, C, and D are the local
counter buses.
The eMIOS200 counter buses are driven by channels in specific locations. The global counter bus is driven
by the channel in channel slot [23]. Counter buses B, C, and D are driven by channels in slots [0], [8], and
[16] respectively. Counter bus A drives all channels. Counter bus B drives channels in slots from [0]
through [7]. Counter bus C drives channels in slots from [8] through [15]. Counter bus D drives channels
in slots from [16] through [23]. Note that the first channel in an 8-channel slice drives the local counter
bus for that slice, therefore this channel should not be assigned to be driven by the same counter bus,
otherwise a loop occurs. The eMIOS200 Interrupt request signal, DMA transfer request signal among
others, are wired to a specific channel, thus the chip integrator should connect those signals having the
eMIOS200 channel configuration in mind.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-25