PXD10RM Datasheet, PDF (308/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

11.8.1.1 Master Mode
In master mode the DSPI can initiate communications with peripheral devices. The DSPI operates as bus
master when the MSTR bit in the DSPIx_MCR is set. The serial communications clock (SCK) is
controlled by the master DSPI. All three DSPI configurations are valid in master mode.
In SPI configuration, master mode transfer attributes are controlled by the SPI command in the current TX
FIFO entry. The CTAS field in the SPI command selects which of the eight DSPIx_CTARs are used to set
the transfer attributes. Transfer attribute control is on a frame by frame basis.
Refer to Section 11.8.3, Serial Peripheral Interface (SPI) Configuration for more details.
11.8.1.2 Slave Mode
In slave mode the DSPI responds to transfers initiated by an SPI master. The DSPI operates as bus slave
when the MSTR bit in the DSPIx_MCR is negated. The DSPI slave is selected by a bus master by having
the slave’s CS0_x asserted. In slave mode the SCK is provided by the bus master. All transfer attributes
are controlled by the bus master, except the clock polarity, clock phase and the number of bits to transfer
which must be configured in the DSPI slave to communicate correctly.
11.8.1.3 Module Disable Mode
The module disable mode is used for MCU power management. The clock to the non-memory mapped
logic in the DSPI is stopped while in module disable mode. The DSPI enters the module disable mode
when the MDIS bit in DSPIx_MCR is set.
Refer to Section 11.8.8, Power Saving Features, for more details on the module disable mode.
11.8.1.4 External Stop Mode
For devices with low-power modes, the DSPI supports the Global Signal Stop Mode mechanism. The
DSPI will not acknowledge the request to enter External Stop Mode until it has reached a frame boundary.
When the DSPI has reached a frame boundary it will halt all operations and indicate that it is ready to have
its clocks shut off. The DSPI exits External Stop Mode and resumes normal operation once the clocks are
turned on. Serial communications or register accesses made while in External Stop Mode are ignored even
if the clocks have not been shut off yet. See Section 11.8.8, Power Saving Features,” for more details on
the External Stop Mode.
11.8.1.5 Debug Mode
The debug mode is used for system development and debugging. If the MCU is stopped by a debugger
while the DSPIx_MCR[FRZ] bit is set, the DSPI halts operation on the next frame boundary and enters a
stopped state. If the MCU is stopped by a debugger while the FRZ bit is cleared, the DSPI behavior is
unaffected and remains dictated by the module-specific mode and configuration of the DSPI. The FRZ bit
operation is only available when the CPU has an active debug mode.
See Figure 11-12 for a state diagram.
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor