PXD10RM Datasheet, PDF (481/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Register address: DMA_Offset + 0x0000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 CX ECX
W
RESET:
00
R
W
RESET:
16 17
GRP3PRI
11
18 19
GRP2PRI
10
20 21
GRP1PRI
01
22 23
GRP0PRI
00
24 25 26 27 28 29 30 31
EML CLM HALT HOE ERG ERC EDB EBW
M
AAG
00000000
= Unimplemented
Figure 15-2. DMA Control Register (DMACR)
Name
CX
ECX
GRP3PRI
GRP2PRI
GRP1PRI
GRP0PRI
Table 15-2. DMA Control Register (DMACR) field descriptions
Description
Cancel Transfer
Error Cancel Transfer
Channel Group 3 Priority
Channel Group 2 Priority
Channel Group 1 Priority
Channel Group 0 Priority
Value
0 Normal operation.
1 Cancel the remaining data transfer. Stop the
executing channel and force the minor loop to be
finished. The cancel takes effect after the last write
of the current read/write sequence. The CXFR bit
clears itself after the cancel has been honored. This
cancel retires the channel normally as if the minor
loop was completed.
0 Normal operation.
1 Cancel the remaining data transfer in the same
fashion as the CX cancel transfer. Stop the
executing channel and force the minor loop to be
finished. The cancel takes effect after the last write
of the current read/write sequence. The ECX bit
clears itself after the cancel cancel has been
honored. In addition to cancelling the transfer, the
ECX treats the cancel as an error condition; thus
updating the DMAES register and generating an
optional error interrupt (see Section 15.2.1.2, DMA
Error Status (DMAES)”).
Group 3 priority level when fixed priority group
arbitration is enabled.
Group 2 priority level when fixed priority group
arbitration is enabled.
Group 1 priority level when fixed priority group
arbitration is enabled.
Group 0 priority level when fixed priority group
arbitration is enabled.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
15-11