PXD10RM Datasheet, PDF (1068/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

30.5.4.3 Leaving Power Saving Modes
In the Stop Mode and the Module Disable Mode the clocks to the QuadSPI module are switched off by
external circuitry. Note that after the QuadSPI module has left these power saving modes and has returned
to normal operation in SFM Mode the execution of the first SFM command is deferred until the clock to
drive that part of the module related to the serial flash device is available. Depending from the point in
time when the first SFM command is programmed the actual execution of that command will start with a
slight delay w.r.t. the re-enabling of the clock signal.
30.5.4.4 Slave Bus Signal Gating
The QuadSPI’s module enable signal is used to gate slave bus signals such as address, byte enable,
read/write and data. This prevents toggling slave bus signals from propagating through parts of the
QuadSPI’s combinational logic and consuming power unless it is a QuadSPI access. The module enable
signal can also be used to gate the clock (ipg_clk_s) to the memory-mapped logic.
30.6 Initialization/Application Information
30.6.1 How to Change Queues - SPI Modes Only
This section presents an example of how to change queues for the QuadSPI. The queues are not part of the
QuadSPI, but the QuadSPI includes features in support of queue management. Queues are supported in
both SPI Modes.
1. Only the last command word from a queue is executed. The EOQ bit in the command word is set
to indicate to the QuadSPI that this is the last entry in the queue.
2. At the end of the transfer, corresponding to the command word with EOQ set is sampled, the EOQ
flag (EOQF) in the QSPI_SPISR is set.
3. The setting of the EOQF flag will disable both serial transmission, and serial reception of data,
putting the QuadSPI in the STOPPED state. The TXRXS bit is negated to indicate the STOPPED
state.
4. The DMA will continue to fill TX FIFO until it is full or step 5 occurs.
5. Disable QuadSPI DMA transfers by disabling the DMA enable request for the DMA channel
assigned to TX FIFO and RX FIFO. This is done by clearing the corresponding DMA enable
request bits in the DMA Controller.
6. Ensure all received data in RX FIFO has been transferred to memory receive queue by reading the
RXCNT in QSPI_SPISR or by checking RFDF in the QSPI_SPISR after each read operation of the
QSPI_POPR.
7. Modify DMA descriptor of TX and RX channels for “new” queues
8. Flush TX FIFO by writing a ‘1’ to the CLR_TXF bit in the QSPI_MCR, Flush RX FIFO by writing
a ‘1’ to the CLR_RXF bit in the QSPI_MCR.
9. Clear transfer count either by setting CTCNT bit in the command word of the first entry in the new
queue or via CPU writing directly to SPI_TCNT field in the QSPI_TCR.
30-64
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor