PXD10RM Datasheet, PDF (268/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

MODE[6]= 1
cycle n
write to A2
Match A1
Selected
Counter Bus
0x000008
0x000006
0x000004
0x000002
0x000001
due to B1 match cycle n-1
Output pin
Match B1
cycle n+1
write to A2
write to B2
Match B1
Match A1
cycle n+2
Match B1
FLAG set event
FLAG pin/register
FLAG clear
Output Disable
A1 value 0x000002
A2 value 0x000002
0x000004
0x000004
0x000006
0x000006
EDPOL = 0
B1 value 0x000008
B2 value 0x000008
0x000006
0x000006
Figure 9-36. OPWMB Mode with Active Output Disable
Figure 9-37 shows a waveform changing from 100% to 0% duty cycle. EDPOL in this case is zero. In this
example B1 is programmed to the same value as the period of the external selected time base.
Selected
cycle 1
counter bus
cycle 2
cycle 3
cycle 4
cycle 5
cycle 6
cycle 7
cycle 8
cycle 9
Output pin
100%
0%
A1 value
A2 value
0x000008 0x000007 0x000006 0x000005 _0x000004 0x000003 0x000002 _0x000001 0x000000
0x000007 0x000006 0x000005 0x000004 _0x000003 0x000002 0x000001 _0x000000
B1 value
0x000008
EDPOL = 0
Prescaler = 1
Figure 9-37. OPWMB Mode from 100% to 0% Duty Cycle
In Figure 9-37 if B1 is set to a value lower than 0x8 it is not possible to achieve 0% duty cycle by only
changing A1 register value. Since B1 matches have precedence over A1 matches the output pin transitions
to the opposite of EDPOL bit at B1 match. Note also that if B1 is set to 0x9, for instance, B1 match does
not occur, thus a 0% duty cycle signal is generated.
9.5.1.2 Input Programmable Filter (IPF)
The IPF ensures that only valid input pin transitions are received by the Unified Channel edge detector. A
block diagram of the IPF is shown in Figure 9-38.
9-42
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor