PXD10RM Datasheet, PDF (190/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

8.4.3.1.3 System Clock Select Status Register (CGM_SC_SS)
Address 0xC3FE_0378
0
1
2
3
4
5
6
7
8
9
10
11
R0
0
0
0
SELSTAT
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
Access: Supervisor read
12
13
14
15
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-5. System Clock Select Status Register (CGM_SC_SS)
This register provides the current system clock source selection.
Table 8-6. System Clock Select Status Register (CGM_SC_SS) Field Descriptions
Field
Description
SELSTAT
System Clock Source Selection Status — This value indicates the clock source for the system clock.
0000 16 MHz internal RC oscillator
0001 Divided 16 MHz internal RC oscillator
0010 4-16 MHz external oscillator
0011 Divided 4-16 MHz external oscillator
0100 Primary FMPLL
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 system clock is disabled
8.4.3.1.4 System Clock Divider Configuration Registers (CGM_SC_DC0…2)
Address 0xC3FE_037C
Access: Supervisor read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
DE0
W
DIV0
0
0
0
DE1
DIV1
Reset 1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
DE2
W
DIV2
0
0
0
0
0
0
0
0
Reset 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-6. System Clock Divider Configuration Registers (CGM_SC_DC0…2)
8-12
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor