PXD10RM Datasheet, PDF (398/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Offset: 0x300
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
000000000000000
HLB
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
R0
W
Reset 0
Field
0
HLB
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
000000000000000
000000000000000
Figure 46.
Figure 12-49. Global Protection Register
Table 12-44. Global Protection Register Field Descriptions
Description
Hard Lock Bit. This bit cannot be cleared once it is set by software. It can only be cleared by a
system reset.
1’b1:All SLB’s are write protected & cannot be modified
1’b0:All SLB’s are accessible & can be modified
12.3.4.40 Soft Lock Bit Register L0
Figure 12-50 represents the Soft Lock Bit Register for Layer0. This is used to protect the 7 control
descriptor layer registers for Layer0.
Offset: 0x304
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0
0000
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 47.
Figure 12-50. Soft Lock Register L0
12-66
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor