PXD10RM Datasheet, PDF (691/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

When the BCC bit is negated, RX15MASK is used as acceptance mask for the Identifier in Message Buffer
15. When the FEN bit in MCR is set (FIFO enabled), the RXG14MASK also applies to element 7 of the
ID filter table. This register has the same structure as the Rx Global Mask Register. It must be programmed
while the module is in Freeze Mode, and must not be modified when the module is transmitting or
receiving frames.
• Address Offset: 0x18
• Reset Value: 0xFFFF_FFFF
18.3.4.7 Error Counter Register (ECR)
This register has 2 8-bit fields reflecting the value of two FlexCAN error counters: Transmit Error Counter
(Tx_Err_Counter field) and Receive Error Counter (Rx_Err_Counter field). The rules for increasing and
decreasing these counters are described in the CAN protocol and are completely implemented in the
FlexCAN module. Both counters are read only except in Freeze Mode, where they can be written by the
CPU.
Writing to the Error Counter Register while in Freeze Mode is an indirect operation. The data is first
written to an auxiliary register and then an internal request/acknowledge procedure across clock domains
is executed. All this is transparent to the user, except for the fact that the data will take some time to be
actually written to the register. If desired, software can poll the register to discover when the data was
actually written.
FlexCAN responds to any bus state as described in the protocol, e.g. transmit ‘Error Active’ or ‘Error
Passive’ flag, delay its transmission start time (‘Error Passive’) and avoid any influence on the bus when
in ‘Bus Off’ state. The following are the basic rules for FlexCAN bus state transitions.
• If the value of Tx_Err_Counter or Rx_Err_Counter increases to be greater than or equal to 128, the
FLT_CONF field in the Error and Status Register is updated to reflect ‘Error Passive’ state.
• If the FlexCAN state is ‘Error Passive’, and either Tx_Err_Counter or Rx_Err_Counter decrements
to a value less than or equal to 127 while the other already satisfies this condition, the FLT_CONF
field in the Error and Status Register is updated to reflect ‘Error Active’ state.
• If the value of Tx_Err_Counter increases to be greater than 255, the FLT_CONF field in the Error
and Status Register is updated to reflect ‘Bus Off’ state, and an interrupt may be issued. The value
of Tx_Err_Counter is then reset to zero.
• If FlexCAN is in ‘Bus Off’ state, then Tx_Err_Counter is cascaded together with another internal
counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
Tx_Err_Counter is reset to zero and counts in a manner where the internal counter counts 11 such
bits and then wraps around while incrementing the Tx_Err_Counter. When Tx_Err_Counter
reaches the value of 128, the FLT_CONF field in the Error and Status Register is updated to be
‘Error Active’ and both error counters are reset to zero. At any instance of dominant bit following
a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zero without
affecting the Tx_Err_Counter value.
• If during system start-up, only one node is operating, then its Tx_Err_Counter increases in each
message it is trying to transmit, as a result of acknowledge errors (indicated by the ACK_ERR bit
in the Error and Status Register). After the transition to ‘Error Passive’ state, the Tx_Err_Counter
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-21