PXD10RM Datasheet, PDF (1258/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Int
Vectors
IRER[17:0]
IRQ_17_16 IRQ_15_08
IRQ_07_00
OR
OR
Interrupt enable
Wakeup enable
WRER[17:0]
OR
Glitch Filter enable
WIFER[17:0]
Flag[17:16]
Flag[15:8]
Edge Detection
Analog Glitch Filter
Flag[7:0]
Pads
Figure 41-13. External Interrupt Pad Diagram
WISR[17:0]
Rising
WIREER[17:0]
Falling
WIFEER[17:0]
Interrupt Edge Enable
All of the external interrupt pads within a single group have equal priority. It is the responsibility of the
user software to search through the group of sources in the most appropriate way for their application.
NOTE
Glitch filter control and pad configuration should be done while the external
interrupt line is disabled in order to avoid erroneous triggering by glitches
caused by the configuration process itself.
41.5.3.1 External Interrupt Management
Each external interrupt can be enabled or disabled independently. This can be performed using a single
rolled up register (Table 41-6). A pad defined as an external interrupt can be configured by the user to
recognize external interrupts with an active rising edge, an active falling edge or both edges being active.
NOTE
Writing a ‘0’ to both IREE[x] and IFEE[x] disables the external interrupt
functionality for that pad completely (i.e. no system wakeup or interrupt will
be generated on any activity on that pad)!
The active IRQ edge is controlled by the users through the configuration of the registers WIREER and
WIFEER.
Each external interrupt supports an individual flag which is held in the flag register (WISR). This register
is a clear-by-write-1 register type, preventing inadvertent overwriting of other flags in the same register.
41-12
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor