PXD10RM Datasheet, PDF (644/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Within the PFLASH2P_LCA's programming model, there are a variety of control and configuration fields.
Some are associated with the operating configuration of the memory banks, while others are related to the
behavior of the AHB master ports.
Due to limitations in the available register bits in the programming model, the PFLASH controllers (both
the single and dual-ported versions) do not provide completely symmetric capabilities for the various
memory banks. In fact, the PFLASH2P_LCA groups together the attributes of the two code flash arrays
attached to bank0 and bank2 of the controller while the configuration of the data flash (bank1) is treated
separately.
First, consider the operating configuration of the flash banks. In particular, there are 4 unique configuration
fields that are associated with a bank. These include all the parameters associated with the timing (read
and write wait states, address pipeline control) as well as the read-while-write control field. Accordingly,
the programming model supports two separate sets of these 4 fields: one for banks 0 and 2 in PFCR0, and
another for bank1 in PFCR1:
// per memory bank configuration controls
b02_apc, b1_apc
// address pipeline control
b02_wwsc, b1_wwsc
// write wait state control
b02_rwsc, b1_rwsc
// read wait state control
b02_rwwc, b1_rwwc
// read-while-write control
where b02 is used to refer to configuration and control information common to banks 0 and 2 while b1
refers to bank1.
Second, there are a total of 6 configuration fields that relate to the operation of the PFLASH2P_LCA’s
page buffers. These fields are defined on a “per port” basis since the control needs to be associated with
the AHB master port and not the destination flash bank. In addition, recall that bank1, connected to the
data flash, does not support prefetching, etc., so the configuration controls for that bank are considerably
reduced compared to banks 0 and 2. The resulting fields are:
// per ahb master port configuration controls
b02_p0_bcfg, b02_p1_bcfg
// page buffer configuration
b02_p0_dpfen, b02_p1_dpfen // data prefetch enable
b02_p0_ipfen, b02_p1_ipfen // inst prefetch enable
b02_p0_pflim, b02_p1_pflim // page buffer prefetch limit
b02_p0_bfen, b02_p1_bfen
// page buffer enable for banks 0,2
b1_p0_bfen, b1_p1_bfen
// page buffer enable for bank1
All these fields are located in the PFCR0 and PFCR1 registers described below.
17.4.3.2.1 Platform Flash Configuration Register 0 (PFCR0)
This register defines the configuration associated with flash memory banks 0 and 2. Collectively, this
corresponds to the “code flash” and the operating configuration defined by certain fields applies to both
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor