PXD10RM Datasheet, PDF (1055/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

System clock
12
3 45 6
SCK
Slave
Sample
Master
Sample
Master
SO
Slave
SO
PCS
t_CSC
t_ASC
t_{CSC = PCS to SCK delay}
t_{ASC = After SCK delay}
Figure 30-30. QuadSPI Modified Transfer Format (MTFE=1, CPHA=1, Fsck = Fsys/4)
30.5.2.8.5 Continuous Selection Format
Some peripherals must be deselected between every transfer. Other peripherals must remain selected
between several sequential serial transfers. The Continuous Selection Format provides the flexibility to
handle both cases. The Continuous Selection Format is enabled for both SPI modes by setting the CONT
bit in the SPI Command.
When the CONT bit = 0, the QuadSPI drives the asserted Chip Select signals to their idle states in between
frames. The idle states of the Chip Select signals are selected by the PCSIS field in the QSPI_MCR.
Figure 30-31 shows the timing diagram for two four-bit transfers with CPHA = 1 and CONT = 0.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-51