PXD10RM Datasheet, PDF (215/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Field
3-15
MOD_PERIOD
16
FM_EN
17-31
INC_STEP
Table 8-29. MR field descriptions (continued)
Description
Modulation period
The MOD_PERIOD field is the binary equivalent of the value modperiod derived from
following formula:
modperiod= -₄----_--^f--^r-_f-^e-_m-^f---_o---_d
where:
fref: represents the frequency of the feedback divider
fmod: represents the modulation frequency
The maximum value of MOD_PERIOD is 0x1000.
Frequency Modulation Enable
The FM_EN enables the frequency modulation.
0 = Frequency Modulation disabled
1= Frequency Modulation enabled
Increment step
The INC_STEP field is the binary equivalent of the value incstep derived from following
formula:
incstep
=
r
ou
nd


1^---0^---2-0^---1-^{-5----–5----}^1-----M^------O^-m---D^--d---P^----E^--M--R^----DI---O^--F--D^{---}
where:
md: represents the peak modulation depth in percentage (Center spread -- pk-pk=+/-md,
Downspread -- pk-pk=-2*md)
MDF: represents the nominal value of loop divider (NDIV in PLL Control Register)
8.9.6 Functional description
8.9.6.1 Normal mode
In Normal Mode the PLL inputs are driven by the CR (see Section 8.9.5.1, Control register (CR)”). This
means that, when the PLL is in lock state, the PLL output clock (PHI) is derived by the reference clock
(CLKIN) through Equation 8-1:
phi= ^c--_I--^lD--^k---_Fi--ⁿ---_-^--_O-^L---_D-^D----_F-^F--
Eqn. 8-1
where the value of IDF, LDF and ODF are set in CR and can be derived from Table 8-25, Table 8-26, and
Table 8-27.
8.9.6.2 Progressive clock cwitching
Progressive clock switching allows to switch system clock to PLL output clock stepping through different
division factors. This means that the current consumption gradually increases and so the voltage regulator
has a better response.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-37