PXD10RM Datasheet, PDF (300/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 11-12. DSPIx_SR Field Descriptions (continued)
Field
14
RFDF
Description
Receive FIFO drain flag. Indicates that the RX FIFO can be drained. Provides a method for the
DSPI to request that entries be removed from the RX FIFO. The bit is set while the RX FIFO is not
empty. The RFDF bit can be cleared by writing 1 to it, or by acknowledgement from the eDMA
controller when the RX FIFO is empty.
0 RX FIFO is empty
1 RX FIFO is not empty
Note: In the interrupt service routine, RFDF must be cleared only after the DSPIx_POPR register
is read.
15
Reserved.
16–19
TXCTR
[0:3]
TX FIFO counter. Indicates the number of valid entries in the TX FIFO. The TXCTR is incremented
every time the DSPI _PUSHR is written. The TXCTR is decremented every time an SPI command
is executed and the SPI data is transferred to the shift register.
20–23
TXNXTPTR
[0:3]
Transmit next pointer. Indicates which TX FIFO entry is transmitted during the next transfer. The
TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to the shift register.
Refer to Section 11.8.3.4, Transmit First In First Out (TX FIFO) Buffering Mechanism for more
details.
24–27
RXCTR
[0:3]
RX FIFO counter. Indicates the number of entries in the RX FIFO. The RXCTR is decremented
every time the DSPI _POPR is read. The RXCTR is incremented after the last incoming databit is
sampled, but before the tASC delay starts. Refer to Section 11.8.5.1, Classic SPI Transfer Format
(CPHA = 0) for details.
28–31
Pop next pointer. Contains a pointer to the RX FIFO entry that is returned when the DSPIx_POPR
POPNXTPTR is read. The POPNXTPTR is updated when the DSPIx_POPR is read. Refer to Section 11.8.3.5,
[0:3]
Receive First In First Out (RX FIFO) Buffering Mechanism for more details.
11.7.2.5 DSPI DMA / Interrupt Request Select and Enable Register (DSPIx_RSER)
The DSPIx_RSER serves two purposes: enables flag bits in the DSPIx_SR to generate DMA requests or
interrupt requests, and selects the type of request to generate. Refer to the bit descriptions for the type of
requests that are supported. Do not write to the DSPIx_RSER while the DSPI is running.
Address: Base + 0x0030
0
1
R _{TCF_} 0
W ^RE
Reset 0 0
2
3
4
5
6
7
8
0
EOQ TFUF
F_RE _RE
0
TFFF
_RE
TFFF
_
DIRS
0
0000000
Access: R/W
9
10
11
12
13
14
15
0
0
0 _RFOF 0 _{RFDF RFDF_}
_RE
_RE DIRS
000000
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Figure 11-6. DSPI DMA / Interrupt Request Select and Enable Register (DSPIx_RSER)
11-18
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor