PXD10RM Datasheet, PDF (708/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

A received Remote Request Frame is not stored in a receive buffer. It is only used to trigger a transmission
of a frame in response. The mask registers are not used in remote frame matching, and all ID bits (except
RTR) of the incoming received frame should match.
In the case that a Remote Request Frame was received and matched an MB, this message buffer
immediately enters the internal arbitration process, but is considered as normal Tx MB, with no higher
priority. The data length of this frame is independent of the DLC field in the remote frame that initiated its
transmission.
If the Rx FIFO is enabled (bit FEN set in MCR), FlexCAN will not generate an automatic response for
Remote Request Frames that match the FIFO filtering criteria. If the remote frame matches one of the
target IDs, it will be stored in the FIFO and presented to the CPU. Note that for filtering formats A and B,
it is possible to select whether remote frames are accepted or not. For format C, remote frames are always
accepted (if they match the ID).
18.4.8.2 Overload Frames
FlexCAN does transmit overload frames due to detection of following conditions on CAN bus:
• Detection of a dominant bit in the first/second bit of Intermission
• Detection of a dominant bit at the 7th bit (last) of End of Frame field (Rx frames)
• Detection of a dominant bit at the 8th bit (last) of Error Frame Delimiter or Overload Frame
Delimiter
18.4.8.3 Time Stamp
The value of the Free Running Timer is sampled at the beginning of the Identifier field on the CAN bus,
and is stored at the end of “move-in” in the TIME STAMP field, providing network behavior with respect
to time.
Note that the Free Running Timer can be reset upon a specific frame reception, enabling network time
synchronization. Refer to TSYN description in Section 18.3.4.2, Control Register (CTRL).
18.4.8.4 Protocol Timing
Figure 18-16 shows the structure of the clock generation circuitry that feeds the CAN Protocol Interface
(CPI) sub-module. The clock source bit (CLK_SRC) in the CTRL Register defines whether the internal
clock is connected to the output of a crystal oscillator (Oscillator Clock) or to the Peripheral Clock
(generally from a PLL). In order to guarantee reliable operation, the clock source should be selected while
the module is in Disable Mode (bit MDIS set in the Module Configuration Register).
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor