PXD10RM Datasheet, PDF (180/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Note: no clock monitor
associated with FMPLL1
FMPLL1
PLL1_Clk
(e.g. 64 MHz)
FXOSC_clk
FIRC_clk
PLL0_Clk
FXOSC_clk_divided
FIRC_clk_divided
PLL0_Clk
FXOSC_clk_divided
FIRC_clk_divided
PLL0_Clk
DCU
Clock
Selector ^{Auxiliary Clk0}
Display
Controller
Unit
Clock
Selector
Clock
Selector
Auxiliary Clk1
/1 to /16
eMIOS_1
(8ch)
Auxiliary Clk2
/1 to /16
eMIOS_0
(16ch)
ip_sync
for emios
OscA
(XOSC)
IRC
Fast
FXOSC_clk
(4-16 MHz)
FIRC_clk
(4-16 MHz)
/1 to /32 ^{FXOSC_clk_divided}
(eg 8 MHz)
FIRC_clk_divided
/1 to /32 _{(eg 16 MHz)}
PLL0_Clk
FMPLL0
(64 Mhz)
FIRC_clk
System
Clock
Selector
FXOSC_clk
sys_clk
Optional Clock to LCD
in Stop and Normal Modes
Clock Monitor
Unit
Reset / INT
(via MC_RGM)
OscB ^SXOSC_clk
(XOSC) (32 KHz)
/1 to /32
SXOSC_clk_divided
Optional Clock to LCD
in standby Modes
IRC
Slow
SIRC_clk
(128 kHz)
/1 to /32
SIRC_clk_divided
Optional Clock to LCD
in Standby Modes
Optional Clock to LCD
in Stop and Normal Modes
FXOSC_clk
FIRC_clk
PLL0_Clk
CLKOUT
Selector
PLL1_clk/2
PLL1_clk
Clock
Selector _{QuadSPI Serial Interface clk}
(eg 64 MHz)
SXOSC_clk
sys_clk
Auxiliary Clk 3
SIRC_clk
sys_clk/2
PLL1_Clk
/1 to /16
/1 to /16
/1 to /16
Core,
Platform
Peripheral
Set 1
Peripheral
Set 2
Peripheral
Set 3
FXOSC_clk_divided
FIRC_clk_divided
SXOSC_clk_divided
SIRC_clk_divided
API/RTC
SIRC_clk_divided _Watchdog
/1, /2, /4, /8 CLKOUT
Figure 8-1. PXD10 system clock generation
8.2 Auxiliary clocks
This device has four auxiliary clocks configurable using the MC_CGM registers. These auxiliary clocks
allow the associated peripherals to operate at clock speeds independent of the system clock (sys_clk). The
peripherals also use the undivided system clock to synchronously interface with the rest of the device. The
auxiliary clock configuration is as follows:
PXD10 Microcontroller Reference Manual, Rev. 1
8-2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice