PXD10RM Datasheet, PDF (682/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Base + 0x0000
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10 11 12
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R _{MDIS FRZ FEN HALT NOT_ 0 SOFT FRZ_ SUPV 0 WRN_ LPM_ 0 DOZE SRX BCC}
RDY
_RST ACK
EN ACK
_DIS
W
RESET:
1
Note
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0
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0 Note
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0 Note 0
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R₀
0 LPRIO AEN 0
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W
_EN
IDAM
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MAXMB
RESET: ₀
0
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1
= Unimplemented or Reserved
Figure 18-5. Module Configuration Register (MCR)
1 _{Reset value of this bit is different on various platforms. Consult the specific MCU documentation to determine its}
value.
2 _{Different on various platforms, but it is always the opposite of the MDIS reset value.}
3 _{Different on various platforms, but it is always the same as the MDIS reset value.}
Field
MDIS
FRZ
FEN
Table 18-8. Module Configuration Register (MCR) field descriptions
Description
Module Disable
This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts down the
clocks to the CAN Protocol Interface and Message Buffer Management sub-modules. This is the
only bit in MCR not affected by soft reset. See Section 18.4.9.2, Module Disable Mode for more
information.
1 = Disable the FlexCAN module
0 = Enable the FlexCAN module
Freeze Enable
The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR Register is set or when
the MCU is stopped by a debugger. When FRZ is asserted, FlexCAN is enabled to enter Freeze
Mode. Negation of this bit field causes FlexCAN to exit from Freeze Mode.
1 = Enabled to enter Freeze Mode
0 = Not enabled to enter Freeze Mode
FIFO Enable
This bit controls whether the FIFO feature is enabled or not. When FEN is set, MBs 0 to 7 cannot
be used for normal reception and transmission because the corresponding memory region
(0x80-0xFF) is used by the FIFO engine. See Section 18.3.3, Rx FIFO Structure and
Section 18.4.7, Rx FIFO for more information.
1 = FIFO enabled
0 = FIFO not enabled
18-12
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor