PXD10RM Datasheet, PDF(318/1332 Page) Freescale Semiconductor, Inc – PXD10 Microcontroller

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

PXD10RM Datasheet, PDF (318/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

◁

11.8.5.2 Classic SPI Transfer Format (CPHA = 1)

This transfer format shown in Figure 11-15 is used to communicate with peripheral SPI slave devices that

require the first SCK_x edge before the first data bit becomes available on the slave SOUT_x pin. In this

format the master and slave devices change the data on their SOUT_x pins on the odd-numbered SCK_x

edges and sample the data on their SIN_x pins on the even-numbered SCK_x edges.

SCK

(CPOL = 0)

SCK

(CPOL = 1)

Master and slave

sample

Master SOUT/

Slave SIN

Master SIN/

Slave SOUT

Master (CPHA = 1): TCF and EOQF are set and RXCTR counter

is updated at last SCK edge of frame (edge 16)

Slave (CPHA = 1): TCF is set and RXCTR counter is updated at

last SCK edge of frame (edge 16)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

PCSx / SS

tCSC

tASC

tDT

MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB

LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB

tCSC = CS to SCK delay.

tASC = After SCK delay.

tDT = Delay after transfer (minimum CS negation time).

Figure 11-15. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 1, FMSZ = 8)

The master initiates the transfer by asserting the CSx signal to the slave. After the tCSC delay has elapsed,

the master generates the first SCK_x edge and at the same time places valid data on the master SOUT_x

pin. The slave responds to the first SCK_x edge by placing its first data bit on its slave SOUT_x pin.

At the second edge of the SCK_x the master and slave sample their SIN_x pins. For the rest of the frame

the master and the slave change the data on their SOUT_x pins on the odd-numbered clock edges and

sample their SIN_x pins on the even-numbered clock edges. After the last clock edge occurs a delay of

tASC is inserted before the master negates the CSx signal. A delay of tDT is inserted before a new frame

transfer can be initiated by the master.

For CPHA = 1 the master EOQF and TCF and slave TCF are set at the last serial clock edge (edge 16) of

Figure 11-15. For CPHA = 1 the master and slave RXCTR counters are updated on the same clock edge.

11-36

PXD10 Microcontroller Reference Manual, Rev. 1

PreliminaryâSubject to Change Without Notice

Freescale Semiconductor

▷