PXD10RM Datasheet, PDF (887/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Chapter 24
Memory Protection Unit (MPU)
24.1 Introduction
The AMBA-AHB Memory Protection Unit (MPU) provides hardware access control for all memory
references generated in the device. Using preprogrammed region descriptors which define memory spaces
and their associated access rights, the MPU concurrently monitors all system bus transactions and
evaluates the appropriateness of each transfer. Memory references that have sufficient access control rights
are allowed to complete, while references that are not mapped to any region descriptor or have insufficient
rights are terminated with a protection error response. This module is commonly included as part of the
platform.
24.1.1 Overview
The MPU module provides the following capabilities:
• Support for 12 program-visible 128-bit (4-word) region descriptors
— Each region descriptor defines a modulo-32 byte space, aligned anywhere in memory
– Region sizes can vary from a minimum of 32 bytes to a maximum of 4 GB
— Two types of access control permissions defined in single descriptor word
– Processors have separate {read, write, execute} attributes for supervisor and user accesses
– Non-processor masters have {read, write} attributes
— Hardware-assisted maintenance of the descriptor valid bit minimizes coherency issues
— Alternate programming model view of the access control permissions word
• Memory-mapped platform device
— Interface to 4 slave AHB ports: flash controller, system RAM controller, IPS peripherals bus,
and QuadSPI module
– Connections to the AHB address phase address and attributes
– Typical location is immediately “downstream” of the platform’s crossbar switch
— Connection to the IPS bus provides access to the MPU’s programming model
A simplified block diagram of the AHB_MPU module is shown in Figure 24-1. The AHB bus slave ports
(s{0,1,2,3}_h*) are shown on the left side of the diagram, the region descriptor registers in the middle and
the IPS bus interface (ips_*) on the right side. The evaluation macro contains the two magnitude
comparators connected to the start and end address registers from each region descriptor (rgdn) as well as
the combinational logic blocks to determine the region hit and the access protection error. For information
on the details of the access evaluation macro, see Section 24.3.1, Access evaluation macro.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
24-1