PXD10RM Datasheet, PDF (965/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

26.6 Memory Map and Register Description
The NDI block contains no memory-mapped registers. Nexus registers are accessed by a development tool
via the JTAG port using a client-select value and a register index. OnCE registers are accessed by loading
the appropriate value in the RS[0:6] field of the OnCE command register (OCMD) via the JTAG port.
26.6.1 Nexus Debug Interface Registers
Table 26-2 shows the NDI registers by client select and index values. OnCE register addressing is
documented in Chapter 19, IEEE 1149.1 Test Access Port Controller (JTAGC).”
Table 26-2. Nexus Debug Interface Registers
Client Select
Index
Register
0bxxxx
0bxxxx
Client-Independent Registers
0
Device ID (DID)¹
127
Port configuration register (PCR)¹
e200z0 Control/Status Registers
0b0000
2
e200z0 development control1 (DC1)
0b0000
3
e200z0 development control2 (DC2)
0b0000
4
e200z0 development status (DS)
0b0000
7
Read/write access control/status (RWCS)
0b0000
9
Read/write access address (RWA)
0b0000
10
Read/write access data (RWD)
0b0000
11
e200z0 watchpoint trigger (PPC_WT)
1 _{Implemented in NPC block. All other registers implemented in e200z0 Nexus2+ block.}
26.6.2 Register Description
This section lists the NDI registers and describes the registers and their bit fields.
26.6.2.1 Nexus Device ID Register (DID)
The NPC device identification register, shown in Figure 26-3, allows the part revision number, design
center, part identification number, and manufacturer identity code of the device to be determined through
the auxiliary output port, and serially through TDO. This register is read-only.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
26-5