PXD10RM Datasheet, PDF (688/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 18-10. Control Register (CTRL) Field Descriptions (continued)
Field
Description
25
BOFF_REC
Bus Off Recovery Mode
This bit defines how FlexCAN recovers from Bus Off state. If this bit is negated, automatic
recovering from Bus Off state occurs according to the CAN Specification 2.0B. If the bit is asserted,
automatic recovering from Bus Off is disabled and the module remains in Bus Off state until the bit
is negated by the user. If the negation occurs before 128 sequences of 11 recessive bits are
detected on the CAN bus, then Bus Off recovery happens as if the BOFF_REC bit had never been
asserted. If the negation occurs after 128 sequences of 11 recessive bits occurred, then FlexCAN
will resynchronize to the bus by waiting for 11 recessive bits before joining the bus. After negation,
the BOFF_REC bit can be re-asserted again during Bus Off, but it will only be effective the next time
the module enters Bus Off. If BOFF_REC was negated when the module entered Bus Off, asserting
it during Bus Off will not be effective for the current Bus Off recovery.
1 = Automatic recovering from Bus Off state disabled
0 = Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B
26
TSYN
Timer Sync Mode
This bit enables a mechanism that resets the free-running timer each time a message is received
in Message Buffer 0. This feature provides means to synchronize multiple FlexCAN stations with a
special “SYNC” message (i.e., global network time). If the FEN bit in MCR is set (FIFO enabled),
MB8 is used for timer synchronization instead of MB0.
1 = Timer Sync feature enabled
0 = Timer Sync feature disabled
27
LBUF
Lowest Buffer Transmitted First
This bit defines the ordering mechanism for Message Buffer transmission. When asserted, the
LPRIO_EN bit does not affect the priority arbitration.
1 = Lowest number buffer is transmitted first
0 = Buffer with highest priority is transmitted first
28
LOM
Listen-Only Mode
This bit configures FlexCAN to operate in Listen Only Mode. In this mode, transmission is disabled,
all error counters are frozen and the module operates in a CAN Error Passive mode [Ref. 1]. Only
messages acknowledged by another CAN station will be received. If FlexCAN detects a message
that has not been acknowledged, it will flag a BIT0 error (without changing the REC), as if it was
trying to acknowledge the message.
1 = FlexCAN module operates in Listen Only Mode
0 = Listen Only Mode is deactivated
29-31
PROPSEG
Propagation Segment
This 3-bit field defines the length of the Propagation Segment in the bit time. The valid
programmable values are 0–7.
Propagation Segment Time = (PROPSEG + 1) * Time-Quanta.
Time-Quantum = one Sclock period.
1 _{One time quantum is equal to the Sclock period.}
18.3.4.3 Free Running Timer (TIMER)
This register represents a 16-bit free running counter that can be read and written by the CPU. The timer
starts from 0x0000 after Reset, counts linearly to 0xFFFF, and wraps around.
The timer is clocked by the FlexCAN bit-clock (which defines the baud rate on the CAN bus). During a
message transmission/reception, it increments by one for each bit that is received or transmitted. When
18-18
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor