PXD10RM Datasheet, PDF (646/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 17-64. PFLASH Configuration Register 0 Field Descriptions (continued)
Field
Description
B02_RWSC
Bank0+2 Read Wait State Control. This field is used to control the number of wait-states to be added
to the flash array access time for reads. This field must be set to a value corresponding to the
operating frequency of the PFLASH and the actual read access time of the PFLASH. The required
settings are documented in the SoC specification. Higher operating frequencies require non-zero
settings for this field for proper flash operation.
0 MHz, < 23 MHz
23 MHz, < 45 MHz
45 MHz, < 68 MHz
68 MHz, < 90 MHz
APC=RWSC=0
APC=RWSC=1
APC=RWSC=2
APC=RWSC=3
This field is set to 0b00010 by hardware reset.
00000 No additional wait-states are added
00001 1 additional wait-state is added
00010 2 additional wait-states are added
...
111111 31 additional wait-states are added
B02_RWWC _{Bank0+2 Read-While-Write Control. This 3-bit field defines the controller response to flash reads}
while the array is busy with a program (write) or erase operation.
0-- Terminate any attempted read while write/erase with an error response
111 Generate a bus stall for a read while write/erase, disable the stall notification interrupt, disable
the abort +
abort notification interrupt
110 Generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable
the abort +
abort notification interrupt
101 Generate a bus stall for a read while write/erase, enable the operation abort, disable the abort
notification
interrupt
100 Generate a bus stall for a read while write/erase, enable the operation abort and the abort
notification interrupt
This field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the
abort and notification interrupts.
B02_P1_BCFG _{Bank0+2, Port 1 Page Buffer Configuration. This field controls the configuration of the four page}
buffers in the PFLASH controller. The buffers can be organized as a “pool” of available resources, or
with a fixed partition between instruction and data buffers.
If enabled, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the group
and the just-fetched entry then marked as most-recently-used. If the flash access is for the
next-sequential line, the buffer is not marked as most-recently-used until the given address produces
a buffer hit.
00 All four buffers are available for any flash access, that is, there is no partitioning of the buffers
based on the access type.
01 Reserved
10 The buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches
and buffers 2 and 3 for data accesses.
11 The buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches
and buffer 3 for data accesses.
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor