PXD10RM Datasheet, PDF (415/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

For 8 bpp, data is in the form shown in Table 12-57.
Table 12-57. Data Layout for 8 bpp
Address offset
0x00
0x04
0x08
[7:0]
pixel0[7:0]
pixel4[7:0]
pixe8[7:0]
[15:8]
pixel1[7:0]
pixel5[7:0]
pixel9[7:0]
[23:16]
pixel2[7:0]
pixel6[7:0]
pixel10[7:0]
[31:24]
pixel3[7:0]
pixel7[7:0]
pixel11[7:0]
For 4 bpp, data is in the form shown in Table 12-58.
Table 12-58. Data Layout for 4 bpp
Address
offset
[3:0]
[7:4]
[11:8]
[15:12] [19:16] [23:20] [27:24] [31:28]
0x00
0x04
0x08
pixel1[3:0] pixel0[3:0] pixel3[3:0] pixel2[3:0] pixel5[3:0] pixel4[3:0] pixel7[3:0] pixel6[3:0]
pixel9[3:0] pixel8[3:0] pixel11[3:0 pixel10[3:0 pixel13[3:0 pixel12[3:0 pixel15[3:0 pixel14[3:0
]
]
]
]
]
]
pixel17[3:0 pixel16[3:0 pixel19[3:0 pixel18[3:0 pixel21[3:0 pixel20[3:0 pixel23
]
]
]
]
]
]
pixel22
For 2 bpp, data is in the form shown in Table 12-59.
Table 12-59. Data Layout for 2bpp
Address
offset
[3:0]
[7:4]
[11:8]
[15:12] [19:16] [23:20] [27:24] [31:28]
0x00
0x04
[pix3,pix2] [pix1,pix0] [pix7,pix6] [pix5,pix4] [pix11,pix10] [pix9,pix8] [pix15,pix14] [pix13,pix12]
[pix19,pix18] pix17,pix16] [pix23,pix22] [pix21,pix20] [pix27,pix26] [pix25,pix24] pix31,pix30] [pix29,pix28]
For 1 bpp, data is in the form shown in Table 12-60.
Table 12-60. Data Layout for 1 bpp
Address offset
0x00
0x04
[7:0]
pixel7-pixel0
pixel39-pixel32
[15:8]
pixel15-pixel8
pixel47-pixel40
[23:16]
pixel23-pixel16
pixel55-pixel48
[31:24]
pixel31-pixel24
pixel63-pixel56
The DCU includes a flag that indicates when it has completed fetching graphics from memory for the
current frame refresh. If required, this flag (DMA_TRANS_FINISH in the INT_STATUS register) can be
used to determine when changes can be made to the source graphic content.
12.4.5.5 Alpha and Chroma-key blending
The blending configuration of each layer is defined by the BB, AB, and TRANS bit fields in register 4 in
the control descriptor for the layer (CTRLDESCLn_4, where n is the layer number). The pixels affected
by the blending configuration can be further selected by registers 5 and 6 in the control descriptor
(CTRLDESCLn_4 and CTRLDESCLn_5). Depending on the priority and placement of the layer (see
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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