PXD10RM Datasheet, PDF (47/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Conditional branches not taken execute in a single clock. Branches with successful target prefetching have an effective execution time
of one clock on e200z0h. All other taken branches have an execution time of two clocks.
Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of
byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow effective single cycle
throughput. Load and store multiple word instructions allow low overhead context save and restore operations. The load/store unit
contains a dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use dependency
does not incur any pipeline bubbles for most cases.
The Condition Register unit supports the condition register (CR) and condition register operations defined by the Power Architecture.
The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point
compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching.
Vectored and autovectored interrupts are supported. Hardware vectored interrupt support is provided to allow multiple interrupt
sources to have unique interrupt handlers invoked with no software overhead.
The CPU includes support for Variable Length Encoding (VLE) instruction enhancements. This allows the classic PowerPC
instruction set to be represented by a modified instruction set made up from a mixture of 16-bit and 32-bit instructions. This results in
a significantly smaller code size footprint without affecting performance noticeably.
The CPU core is enhanced by an additional interrupt source—Non Maskable Interrupt. This interrupt source is routed directly from
package pins, via edge detection logic in the SIU to the CPU, bypassing the Interrupt Controller completely. Once the edge detection
logic is programmed, it can not be disabled, except by reset. The Non Maskable Interrupt is, as the name suggests, completely
un-maskable and when asserted will always result in the immediate execution of the respective interrupt service routine. The Non
maskable interrupt is not guaranteed to be recoverable.
The CPU core has an additional ‘Wait for Interrupt’ instruction that is used in conjunction with low power STOP mode. When Low
Power Stop mode is selected, this instruction is executed to allow the system clock to be stopped. An external interrupt source or the
system wake-up timer is used to restart the system clock and allow the CPU to service the interrupt.
Additional features include:
• Load/store unit
— 1-cycle load latency
— Misaligned access support
— No load-to-use pipeline bubbles
• Thirty-two 32-bit general purpose registers (GPRs)
• Separate instruction bus and load/store bus Harvard architecture
• Reservation instructions for implementing read-modify-write constructs