PXD10RM Datasheet, PDF (480/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

has only one group (0). Group 3 contains channels 63-48, group 2 contains channels 47-32, group 1
contains channels 31-16, and group 0 contains channels 15-0.
Arbitration within a group can be configured to use either a fixed-priority or a round-robin selection. In
fixed-priority arbitration, the highest priority channel requesting service is selected to execute. The
priorities are assigned by the channel priority registers (see Section 15.2.1.17, DMA Channel n Priority
(DCHPRIn), n = 0,..., {15,31,63}”). In round-robin arbitration mode, the channel priorities are ignored and
the channels within each group are cycled through without regard to priority.
The group priorities operate in a similar fashion. In group fixed-priority arbitration mode, channel service
requests in the highest priority group are executed first where priority level 3 is the highest and priority
level 0 is the lowest. The group priorities are assigned in the GRPnPri registers. All group priorities must
have unique values prior to any channel service requests occur, otherwise a configuration error will be
reported. Unused group priority registers, per configuration, are unimplemented in the DMACR. In group
round-robin mode, the group priorities are ignored and the groups are cycled through without regard to
priority.
Minor loop offsets are address offset values added to the final source address (saddr) or destination address
(daddr) upon minor loop completion. When minor loop offsets are enabled, the minor loop offset (mloff)
is added to the final source address (saddr), or the final destination address (daddr), or both prior to the
addresses being written back into the TCD. If the major loop is complete, the minor loop offset is ignored
and the major loop address offsets (slast and dlast_sga) are used to compute the next saddr and daddr
values.
When minor loop mapping is enabled (DMACR[EMLM] = 1), TCDn word2 is redefined. A portion of
TCDn word2 is used to specify multiple fields: an source enable bit (smloe) to specify the minor loop offset
should be applied to the source address (saddr) upon minor loop completion, an destination enable bit
(dmloe) to specify the minor loop offset should be applied to the destination address (daddr) upon minor
loop completion, and the sign extended minor loop offset value (mloff). The same offset value (mloff) is
used for both source and destination minor loop offsets. When either minor loop offset is enabled (smloe
set or dmloe set), the nbytes field is reduced to 10 bits. When both minor loop offsets are disabled (smloe
cleared and dmloe cleared), the nbytes field is a 30-bit vector.
When minor loop mapping is disabled (DMACR[EMLM] = 0), all 32 bits of TCDn word2 are assigned to
the nbytes field. See Section 15.2.1.18, Transfer Control Descriptor (TCD),” for more details.
See Figure 15-2 and Table 15-2 for the DMACR definition.
15-10
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor