PXD10RM Datasheet, PDF (114/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

2. If user mode is not allowed, user writes to all areas will assert a transfer error and the writes will
be blocked.
3. If accessing the reserved area #2, a transfer error will be asserted.
4. If accessing unimplemented 32-bit registers in area #4 and area #5 a transfer error will be asserted.
5. If writing to a register in area #1 and area #3 with Soft Lock Bit set for any of the affected bytes a
transfer error is asserted and the write will be blocked. Also the complete write operation to
non-protected bytes in this word is ignored.
6. If writing to a Soft Lock Register in area #4 with the Hard Lock Bit being set a transfer error is
asserted.
7. Any write operation in any access mode to area #3 while Hard Lock Bit GCR.HLB is set
4.1.5 Reset
The reset state of each individual bit is shown within the Register Description section (See Section 4.1.3.2,
Register Description”). In summary, after reset, locking for all MRn registers is disabled. The registers can
be accessed in Supervisor Mode only.
4.2 Software Watchdog Timer (SWT)
4.2.1 Overview
The Software Watchdog Timer (SWT) is a peripheral module that can prevent system lockup in situations
such as software getting trapped in a loop or if a bus transaction fails to terminate. When enabled, the SWT
requires periodic execution of a watchdog servicing sequence. Writing the sequence resets the timer to a
specified time-out period. If this servicing action does not occur before the timer expires the SWT
generates an interrupt or hardware reset. The SWT can be configured to generate a reset or interrupt on an
initial time-out, a reset is always generated on a second consecutive time-out.
The SWT provides a window functionality. When this functionality is programmed, the servicing action
should take place within the defined window. When occuring outside the defined period, the SWT will
generate a reset.
4.2.2 Features
The SWT has the following features:
• 32-bit time-out register to set the time-out period
• The unique SWT counter clock is the undivided low power internal oscillator (IRC 128 khz), no
other clock source can be selected
• Programmable selection of window mode or regular servicing
• Programmable selection of reset or interrupt on an initial time-out
• Master access protection
• Hard and soft configuration lock bits
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor