PXD10RM Datasheet, PDF (428/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

12.4.7 CLUT/Tile RAM
The internal tile memory and color look up table (CLUT) memory share a common block of RAM internal
to the DCU. Color information in this RAM is always stored as aligned 32-bit words where the
most-significant byte is always 0x00, the next byte contains the red component, the next the green
component and the least significant byte the blue component (0x00RRGGBB).
This memory block can be used to store either color look-up tables or graphics for use as a tile on a layer.
The content of the RAM at a specific address is defined by the control descriptor of a layer. The LUOFFS
bit field in the layer control descriptor defines the starting address of the area, and the BPP and TILE_EN
bit fields define what type of use the RAM area has.
In Figure 12-75 three areas of the RAM are defined for different purposes. Area A is used by layer 1 as a
CLUT for its 4 bpp graphic. Area B is use by layer 5 as a store for its tile graphic. Area C is used by layers
2, 7, and 9 as a CLUT for their 8 bpp graphics.
CLUT/Tile RAM
16 palette entries
A
64 pixel entries
for 8 x 8 tile
B
256 palette entries
C
Figure 12-75. An example of use for the CLUT/Tile RAM
The CLUT/Tile RAM is mapped in the DCU 16K memory space from address 0x2000 to 0x3FFF. This
gives 2048 entries, which provides up to eight full CLUTs for 8 bpp layers.
The CLUT/Tile RAM may be written at any time when the TFT LCD panel is not being driven with data.
This means that the RAM can be modified when the DCU is not enabled and during the vertical blanking
period.
12-96
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor