PXD10RM Datasheet, PDF (106/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

• Once configured lock bits can be protected from changes
4.1.1.3 Modes of Operation
The Register Protection module is operable when the module under protection is operable. For further
details about the availability please see the module’s chapter in this document.
4.1.2 External Signal Description
There are no external signals.
4.1.3 Memory Map and Register Description
This section provides a detailed description of the memory map of a module using the Register Protection.
The original 16 KB module memory space is divided into five areas as shown in Figure 4-2.
Base + 0x0000
Module register space
6 KB
Area 1
Base + 0x1800
Base + 0x2000
Base + 0x3800
Base + 0x3E00
Base + 0x3FFF
2 KB Reserved
Mirror module register space
with user defined
soft locking function
6 KB
1.5 KB Lock Bits
512 bytes Configuration
Area 2
Area 3
Area 4
Area 5
Figure 4-2. Register Protection Memory Diagram
Area 1 is 6 KB large and holds the normal functional module registers and is transparent for all read/write
operations.
Area 2 is 2 KB starting at address 0x1800 is a reserved area, which shall not be accessed.
Area 3 is 6 KB large, starting at address 0x2000 and is a mirror of area 1. A read/write access to these
0x2000+X addresses will read/write the register at address X. As a side effect, a write access to address
0x2000+X will set the optional Soft Lock Bits for this address X in the same cycle as the register at address
X is written. Not all registers in area 1 need to have protection defined by associated Soft Lock Bits. For
PXD10 Microcontroller Reference Manual, Rev. 1
4-2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice