PXD10RM Datasheet, PDF (1234/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 39-3. STM_CNT Field Descriptions
Field
Description
CNT Timer count value used as the time base for all channels. When enabled, the counter increments at the
rate of the system clock divided by the prescale value.
39.3.2.3 STM Channel Control Register (STM_CCRn)
The STM Channel Control Register (STM_CCRn) has the enable bit for channel n of the timer.
Offset 0x10+0x10*n
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 39-4. STM Channel Control Register (STM_CCRn)
Table 39-4. STM_CCRn Field Descriptions
Field
Description
CEN
Channel Enable.
0 = The channel is disabled.
1 = The channel is enabled.
39.3.2.4 STM Channel Interrupt Register (STM_CIRn)
The STM Channel Interrupt Register (STM_CIRn) has the interrupt flag for channel n of the timer.
39-4
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor