PXD10RM Datasheet, PDF (1079/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 30-53. Instruction Code Options on Winbond Devices (continued)
Instruction
Byte 3
Byte 2
Byte 1
Code
76543210765432107654321 0
9Fh
Size
FFh
opt. FFh²
1 _{‘read’ bit controls if 8 SCLK clocks are added to read the device ID, equivalent to Size = 1 (1byte to read)}
2 _{To reset continuous read mode while in Dual I/O operations, set size to ‘1’ and Byte 1 to FFh (ICR = 0001FFFFh).}
To reset the continuous read mode while in Quad I/O operations, only instruction FFh is required (ICR =
000000FFh).
30.7.2 Serial Flash Clock Frequency Limitations
Certain commands of the Winbond serial flash devices are limited in the frequency applied to the serial
flash device on command execution. To allow for higher clock speeds for the remaining commands the
serial flash device clock can be divided by 2 (half speed) when executing such a command limited in
frequency by setting the QSPI_SMPR[HSENA] bit. Refer to Table 30-52 for the commands affected.
30.8 Internal Sampling of Serial Flash Input Data
Depending from the actual implementation there is a delay between the internal clocking in the QuadSPI
module and the external serial flash device. This means that the incoming data from the serial flash appear
this delay later in time at the QuadSPI sampling logic w.r.t. internal reference clock. Refer to Figure 30-37
for an overview of this scheme.
QUADSPI
SFM
Clock Gen
1
SCK - Serial Flash Clock
2
SFM
SI_IO[0:3] - Serial Flash Data
Sampling
5
4
Serial Flash
Clock
3
Data
Out
Figure 30-37. Serial Flash Sampling Clock Overview
NOTE
The arrival of the serial flash data in the sampling stage of the QuadSPI
module are given in fig Figure 30-38 below. Note that the amount of the
total delay t_Del,total is very specific to the characteristics of the actual
implementation.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-75