PXD10RM Datasheet, PDF (529/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

programming model must match the size of the register, e.g., an n-bit register only supports n-bit writes,
etc. Attempted writes of a different size than the register width produce an error termination of the bus
cycle and no change to the targeted register.
16.4.2.1 Processor Core Type (PCT) Register
The PCT is a 16-bit read-only register specifying the architecture of the processor core in the device. The
state of this register is defined by a module input signal; it can only be read from the IPS programming
model. Any attempted write is ignored.
See Figure 16-1 and Table 16-2 for the Processor Core Type definition.
Register address: ECSM Base + 0x00
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
PCT[0:15]
W
RESET: 1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
= Unimplemented
Figure 16-1. Processor Core Type (PCT) Register
Table 16-2. Processor Core Type (PCT) Field Descriptions
Name
Description
0-15 Processor Core Type
PCT[0:15] 0xE012 identifies the e200z0h Power Architecture processor core.
16.4.2.2 Revision (REV) Register
The REV is a 16-bit read-only register specifying a revision number that can only be read from the IPS
programming model. Any attempted write is ignored.
See Figure 16-2 and Table 16-3 for the Revision definition.
Register address: ECSM Base + 0x02
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
REV[0:15]
W
RESET:
REV[0:15]
= Unimplemented
Figure 16-2. Revision (REV) Register
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
16-3