PXD10RM Datasheet, PDF (509/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 15-28. TCDn Word 7 (TCDn.{biter, control/status}) field descriptions (continued)
Name
int_maj
Description
Value
Enable an interrupt when major iteration
count completes
If this flag is set, the channel generates an interrupt
request by setting the appropriate bit in the DMAINT
register when the current major iteration count
reaches zero.
start
Channel start
0 The end-of-major loop interrupt is disabled.
1 cThe end-of-major loop interrupt is enabled.
If this flag is set, the channel is requesting service.
The DMA hardware automatically clears this flag
after the channel begins execution.
0 The channel is not explicitly started.
1 The channel is explicitly started via a software
initiated service request.
15.3 Functional description
This section provides an overview of the microarchitecture and functional operation of the DMA module.
15.3.1 DMA microarchitecture
The DMA module is partitioned into two major modules: the DMA engine and the transfer control
descriptor local memory. Additionally, the DMA engine is further partitioned into four submodules, which
are detailed below.
• DMA engine
— addr_path: This module implements registered versions of two channel transfer control
descriptors: channel "x" and channel “y”, and is responsible for all the master bus address
calculations. All the implemented channels provide the exact same functionality. This
hardware structure allows the data transfers associated with one channel to be preempted after
the completion of a read/write sequence if a higher priority channel service request is asserted
while the first channel is active. Once a channel is activated, it runs until the minor loop is
completed unless preempted by a higher priority channel. This capability provides a
mechanism (optionally enabled by DCHPRIn[ECP]) where a large data move operation can be
preempted to minimize the time another channel is blocked from execution.
When any other channel is activated, the contents of its transfer control descriptor is read from
the local memory and loaded into the registers of the other addr_path.channel_{x,y}. Once the
inner minor loop completes execution, the addr_path hardware writes the new values for the
TCDn.{saddr, daddr, citer} back into the local memory. If the major iteration count is
exhausted, additional processing is performed, including the final address pointer updates,
reloading the TCDn.citer field, and a possible fetch of the next TCDn from memory as part of
a scatter/gather operation.
— data_path: This module implements the actual bus master read/write datapath. It includes 32
bytes of register storage (matching the maximum transfer size) and the necessary mux logic to
support any required data alignment. The AMBA-AHB read data bus is the primary input, and
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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