PXD10RM Datasheet, PDF (407/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

The number of pixel data slots in the horizontal timing diagram is defined by the width of the panel. The
number of line data slots is defined by the height of the panel. Both of these values are defined in the
DISP_SIZE register (DELTA_X, DELTA_Y). The width of the panel must always be defined as a multiple
of 16.
The timing of the pixel clock is defined by the DIV_RATIO register and the frequency of the clock
supplied to the DCU.
In addition to defining the number and timing of pixels in each line and the number of lines, it is normal
for TFT LCD panel manufacturers to define other timing signals in terms of pixel clock periods or of the
number of horizontal lines. The DCU also follows this convention.
If the TFT LCD panel requires a horizontal synchronizing signal (HSYNC) and/or a data enable signal,
then these can be configured using the fields in the HSYN_PARA register. HSYNC provides a pulse to
give the panel notice that the next line of pixel data is about to start, and the data enable signal indicates
when that data is present. The PW_H bit field indicates the width of the HSYNC pulse, in pixel data clock
periods. The BP_H bit field defines the delay between the end of the HSYNC pulse and the start of the
data enable signal (and pixel data delivery), in pixel clock periods. The FP_H bit field defines the delay
between the end of the data enable signal (and pixel data delivery) and the next HSYNC pulse, in pixel
clock periods. FP_H and BP_H have minimum values of 1.
If the TFT LCD panel requires a vertical synchronizing signal (VSYNC), then this can be configured using
the fields in the VSYN_PARA register. VSYNC provides a pulse to give the panel notice that the next
frame of pixel data lines is about to start, and the panel defines delays before and after this pulse, in terms
of pixel clock periods. The PW_V bit field indicates the width of the VSYNC pulse in horizontal line
periods. The BP_V bit field defines the delay between the end of the VSYNC pulse and the start of the
next pixel data (data enable signal), in horizontal line periods. The FP_V bit field defines the delay
between the end of the last pixel data (data enable signal) and the next VSYNC pulse, in horizontal line
periods. FP_V and BP_V have minimum values of 1.
The polarity of all these signals, including the pixel data itself, may be inverted by using the control bits
in the SYN_POL register.
The refresh rate for the panel can be calculated using Equation 12-54 and Equation 12-55 below.
where:
RR
=
---------------------------------------------------------------------------^p--ⁱ-^x---^_--^c--^l-^k---------------------------------------------------------------------------
DELTA_X + FP_H + PW_H + BP_H  DELTA_Y + FP_V + PW_V + BP_V
pix_clk is the pixel clock
DELTA_X is the horizontal resolution (in pixels)
DELTA_Y is the vertical resolution (in pixels)
FP_H is the hsync front porch pulse width (in pixel clock cycles)
BP_H is the hsync back porch pulse width (in pixel clock cycles)
PW_H is the hsync active pulse width (in pixel clock cycles)
FP_V is the vsync front porch pulse width (in pixel clock cycles)
BP_V is the vsync back porch pulse width (in pixel clock cycles)
PW_V is the vsync active pulse width (in pixel clock cycles)
Eqn. 12-54
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
12-75