PXD10RM Datasheet, PDF (620/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 17-51. UT0 field descriptions (continued)
Field
Description
29 AIS: Array Integrity Sequence (Read/Write)
AIS determines the address sequence to be used during array integrity checks or Margin Mode.
The default sequence (AIS=0) is meant to replicate sequences normal user code follows, and thoroughly
checks the read propagation paths. This sequence is proprietary.
The alternative sequence (AIS=1) is just logically sequential.
It should be noted that the time to run a sequential sequence is significantly shorter than the time to run
the proprietary sequence. Only the Sequential Mode is allowed in Margin Mode.
This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data
while writing has no effect.
0: Array Integrity sequence is proprietary sequence.
1: Array Integrity sequence or Margin Mode sequence is sequential.
31 AIE: Array Integrity Enable (Read/Write)
AIE set to 1 starts the Array Integrity Check done on all selected and unlocked blocks.
The pattern is selected by AIS, and the MISR (UMISR0-4) can be checked after the operation is complete,
to determine if a correct signature is obtained.
AIE can be set only if MCR.ERS, MCR.PGM and MCR.EHV are all low.
0: Array Integrity Checks, Margin Mode, and ECC Logic Checks are not enabled.
1: Array Integrity Checks, Margin Mode, and ECC Logic Checks are enabled.
31 AID: Array Integrity Done (Read Only)
AID will be cleared upon an Array Integrity Check being enabled (to signify the operation is on-going).
Once completed, AID will be set to indicate that the Array Integrity Check is complete. At this time the
MISR (UMISR0-4) can be checked.
0: Array Integrity Check is on-going.
1: Array Integrity Check is done.
17.3.6.12 User Test 1 register (UT1)
Address Offset: 0x00040
Reset value: 0x00000000
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DAI31 DAI30 DAI29 DAI28 DAI27 DAI26 DAI25 DAI24 DAI23 DAI22 DAI21 DAI20 DAI19 DAI18 DAI17 DAI16
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DAI15 DAI14 DAI13 DAI12 DAI11 DAI10 DAI09 DAI08 DAI07 DAI06 DAI05 DAI04 DAI03 DAI02 DAI01 DAI00
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 17-35. User Test 1 register (UT1)
The User Test 1 Register allows to enable the checks on the ECC logic related to the 32 LSB of the Double
Word.
The User Test 1 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns
indeterminate data while writing has no effect.
17-70
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor