PXD10RM Datasheet, PDF (650/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 17-65. PFLASH Configuration Register 1 Field Descriptions (continued)
Field
B1_RWWC
Description
Bank1 Read-While-Write Control. This 3-bit field defines the controller response to flash reads
while the array is busy with a program (write) or erase operation.
0-- Terminate any attempted read while write/erase with an error response
111 Generate a bus stall for a read while write/erase, disable the stall notification interrupt, disable
the abort +
abort notification interrupt
110 Generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable
the abort +
abort notification interrupt
101 Generate a bus stall for a read while write/erase, enable the operation abort, disable the abort
notification
interrupt
100 Generate a bus stall for a read while write/erase, enable the operation abort and the abort
notification interrupt
This field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the
abort and notification interrupts.
B1_P1_BFE
This field is ignored in single bank flash configurations.
Bank1, Port 1 Buffer Enable. This bit enables or disables read hits from the 128-bit holding register.
It is also used to invalidate the contents of the holding register. This bit is set by hardware reset,
enabling the use of the holding register.
B1_P0_BFE
0 The holding register is disabled from satisfying read requests.
1 The holding register is enabled to satisfy read requests on hits.
Bank1, Port 0 Buffer Enable. This bit enables or disables read hits from the 128-bit holding register.
It is also used to invalidate the contents of the holding register. This bit is set by hardware reset,
enabling the use of the holding register.
0 The holding register is disabled from satisfying read requests.
1 The holding register is enabled to satisfy read requests on hits.
17.4.3.2.3 Platform Flash Access Protection Register (PFAPR)
The PFLASH Access Protection Register (PFAPR) is used to control read and write accesses to the flash
based on system master number. Prefetching capabilities are defined on a per master basis. This register
also defines the arbitration mode between the 2 AHB ports for the PFLASH2P_LCA. The register is
described below in Figure 17-46 and Table 17-66.
The contents of the register are loaded from location 0x203E00 of the shadow region in the code flash
(bank0) array at reset. To temporarily change the values of any of the fields in the PFAPR, a write to the
IPS-mapped register is performed. To change the values loaded into the PFAPR at reset, the word location
at address 0x203E00 of the shadow region in the flash array must be programmed using the normal
17-100
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor