PXD10RM Datasheet, PDF (539/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 16-10. ECC Error Generation (EEGR) Field Descriptions (continued)
Name
Description
3
Force RAM One 1-bit Data Inversion
FR11BI 0 = No RAM single 1-bit data inversion is generated.
1 = One 1-bit data inversion in the RAM is generated.
The assertion of this bit forces the RAM controller to create one 1-bit data inversion, as defined by the
bit position specified in ERRBIT[0:6], on the first write operation after this bit is set.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being
set again to properly re-enable the error generation logic.
This bit can only be set if the same SoC configurable input enable signal (as that used to enable single-bit
correction reporting) is asserted.
6
FRCNCI
Note: The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are
{0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior.
Force RAM Continuous Noncorrectable Data Inversions
0 = No RAM continuous 2-bit data inversions are generated.
1 = 2-bit data inversions in the RAM are continuously generated.
The assertion of this bit forces the RAM controller to create 2-bit data inversions, as defined by the bit
position specified in ERRBIT[0:6] and the overall odd parity bit, continuously on every write operation.
After this bit has been enabled to generate another continuous noncorrectable data inversion, it must be
cleared before being set again to properly re-enable the error generation logic.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
7
FR1NCI
Note: The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are
{0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior.
Force RAM One Noncorrectable Data Inversions
0 = No RAM single 2-bit data inversions are generated.
1 = One 2-bit data inversion in the RAM is generated.
The assertion of this bit forces the RAM controller to create one 2-bit data inversion, as defined by the
bit position specified in ERRBIT[0:6] and the overall odd parity bit, on the first write operation after this
bit is set.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again
to properly re-enable the error generation logic.
Note: The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are
{0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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