PXD10RM Datasheet, PDF (255/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

As the internal counter EMIOSCNT[n] continues to run in all modes (except for GPIO mode), it is possible
to use this as a time base if the resource is not used in the current mode.
In order to provide smooth waveform generation even if A and B registers are changed on the fly, it is
available the MCB, OPWFMB, and OPWMB modes. In these modes A and B registers are double
buffered.
9.5.1.1.1 General purpose Input/Output mode (GPIO) Mode
In GPIO mode, all input capture and output compare functions of the UC are disabled, the internal counter
(EMIOSCNT[n] register) is cleared and disabled. All control bits remain accessible. In order to prepare
the UC for a new operation mode, writing to registers EMIOSA[n] or EMIOSB[n] stores the same value
in registers A1/A2 or B1/B2, respectively. Writing to register EMIOSALTA[n] stores a value only in
register A2.
MODE[6] bit selects between input (MODE[6] = 0) and output (MODE[6] = 1) modes.
It is required that when changing MODE[0:6], the application software goes to GPIO mode first in order
to reset the UC’s internal functions properly. Failure to do this could lead to invalid and unexpected output
compare or input capture results or the FLAGs being set incorrectly.
In GPIO input mode (MODE[0:6]=0000000), the FLAG generation is determined according to EDPOL
and EDSEL bits and the input pin status can be determined by reading the UCIN bit.
In GPIO output mode (MODE[0:6]=0000001), the Unified Channel is used as a single output port pin and
the value of the EDPOL bit is permanently transferred to the output flip-flop.
9.5.1.1.2 Single Action Input Capture (SAIC) Mode
In SAIC mode (MODE[0:6]=0000010), when a triggering event occurs on the input pin, the value on the
selected time base is captured into register A2. The FLAG bit is set along with the capture event to indicate
that an input capture has occurred. Register EMIOSA[n] returns the value of register A2. As soon as the
SAIC mode is entered coming out from GPIO mode the channel is ready to capture events. The events are
captured as soon as they occur thus reading register A always returns the value of the latest captured event.
Subsequent captures are enabled with no need of further reads from EMIOSA[n] register. The FLAG is set
at any time a new event is captured.
The input capture is triggered by a rising, falling or either edges in the input pin, as configured by EDPOL
and EDSEL bits in EMIOSC[n] register.
Figure 9-21 and Figure 9-22 shows how the Unified Channel can be used for input capture.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-29