PXD10RM Datasheet, PDF (649/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 17-65. PFLASH Configuration Register 1 Field Descriptions
Field
B1_APC
Description
Bank1 Address Pipelining Control. This field is used to control the number of cycles between flash
array access requests. This field must be set to a value appropriate to the operating frequency of
the PFLASH. The required settings are documented in the SoC specification. Higher operating
frequencies require non-zero settings for this field for proper flash operation. This field is set to
0b00010 by hardware reset.
00000
00001
00010
...
11110
11111
Accesses may be initiated on consecutive (back-to-back) cycles
Access requests require one additional hold cycle
Access requests require two additional hold cycles
Access requests require 30 additional hold cycles
Access requests require 31 additional hold cycles
B1_WWSC
This field is ignored in single bank flash configurations.
Bank1 Write Wait State Control. This field is used to control the number of wait-states to be added
to the flash array access time for writes. This field must be set to a value appropriate to the
operating frequency of the PFLASH. The required settings are documented in the SoC
specification. Higher operating frequencies require non-zero settings for this field for proper flash
operation. This field is set to an appropriate value by hardware reset. This field is set to 0b00010 by
hardware reset.
00000 No additional wait-states are added
00001 1 additional wait-state is added
00010 2 additional wait-states are added
...
111111 31 additional wait-states are added
B1_RWSC
This field is ignored in single bank flash configurations.
Bank1 Read Wait State Control. This field is used to control the number of wait-states to be added
to the flash array access time for reads. This field must be set to a value corresponding to the
operating frequency of the PFLASH and the actual read access time of the PFLASH. The required
settings are documented in the SoC specification. Higher operating frequencies require non-zero
settings for this field for proper flash operation.
Shown below are the maximum operating frequencies for legal APC and RWSC settings based on
estimated low-cost flash access times at 150C. The integrator is strongly encouraged to verify
these settings based on actual silicon results.
0 MHz, < 23 MHz
23 MHz, < 45 MHz
45 MHz, < 68 MHz
68 MHz, < 90 MHz
APC=RWSC=0
APC=RWSC=1
APC=RWSC=2
APC=RWSC=3
This field is set to 0b00010 by hardware reset.
00000 No additional wait-states are added
00001 1 additional wait-state is added
00010 2 additional wait-states are added
...
111111 31 additional wait-states are added
This field is ignored in single bank flash configurations.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
17-99