PXD10RM Datasheet, PDF (315/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 11-23. Delay after Transfer Computation Example in TSB Configuration
PDT field
t_DT1 (Tsck)
0²
0
1
1
2
2
3
3
4
1
1
3
5
7
2
2
6
10
14
3
4
12
20
28
4
8
24
40
56
5
16
48
80
112
6
32
96
160
224
7
64
192
320
448
8
128
384
640
896
9
256
768
1280
1792
10
512
1536
2560
3584
11
1024
3072
5120
7168
12
2048
6144
10240
14336
13
4096
12288
20480
28672
14
8192
24576
40960
57344
15
16384
49152
81920
114688
1 _{Some values are not reachable (i. e. 9, 11, 13, 15, 17, 18, 19...). To calculate these values, please}
see Equation 11-3.
2 _{The values in this row were rounded to the next integer value.}
11.8.5 Transfer Formats
The SPI serial communication is controlled by the serial communications clock (SCK_x) signal and the
CSx signals. The SCK_x signal provided by the master device synchronizes shifting and sampling of the
data by the SIN_x and SOUT_x pins. The CSx signals serve as enable signals for the slave devices.
When the DSPI is the bus master, the CPOL and CPHA bits in the DSPI clock and transfer attributes
registers (DSPIx_CTARn) select the polarity and phase of the serial clock, SCK_x. The polarity bit selects
the idle state of the SCK_x. The clock phase bit selects if the data on SOUT_x is valid before or on the first
SCK_x edge.
When the DSPI is the bus slave, CPOL and CPHA bits in the DSPIx_CTAR0 (SPI slave mode) select the
polarity and phase of the serial clock. Even though the bus slave does not control the SCK signal, clock
polarity, clock phase and number of bits to transfer must be identical for the master device and the slave
device to ensure proper transmission.
The DSPI supports four different transfer formats:
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
11-33