PXD10RM Datasheet, PDF (469/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

USER Mode Program Model
General Registers
Condition Register
CR
Count Register
CTR
SPR 9
General-Purpose
Registers
GPR0
GPR1
Link Register
LR
SPR 8
GPR31
XER
XER
SPR 1
Cache Register (Read-only)
Cache Configuration
L1CFG0 SPR 515
Figure 14-3. e200z0h User Mode Program Model
14.3.1 Unimplemented SPRs and Read-only SPRs
e200z0h fully decodes the SPR field of the mfspr and mtspr instructions. If the SPR specified is undefined
and not privileged, an illegal instruction exception is generated. If the SPR specified is undefined and
privileged and the CPU is in user mode (MSR[PR=1]), a privileged instruction exception is generated. If
the SPR specified is undefined and privileged and the core is in supervisor mode (MSR[PR=0]), an illegal
instruction exception is generated.
For the mtspr instruction, if the SPR specified is read-only and not privileged, an illegal instruction
exception is generated. If the SPR specified is read-only and privileged and the core is in user mode
(MSR[PR=1]), a privileged instruction exception is generated. If the SPR specified is read-only and
privileged and the core is in supervisor mode (MSR[PR=0]), an illegal instruction exception is generated.
14.4 Instruction summary
e200z0h supports all VLE instructions described in the PowerPC™ VLE APU Definition version 1.2
together with the additional instructions for context save/restore.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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