PXD10RM Datasheet, PDF (630/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

17.3.7.4 User Test Mode
User Test Mode is a mode, that customers can put the Flash Module in, to do specific tests to check the
integrity of the Flash Module.
Three kinds of Test can be performed:
• Array Integrity Self Check
• Margin Mode Read
• ECC Logic Check
The User Test Mode is equivalent to a Modify operation: read accesses attempted by the user during User
Test Mode generates a Read-While-Write Error (RWE of MCR set).
It is not allowed to perform User Test operations on the Test and Shadow blocks.
17.3.7.4.1 Array Integrity Self Check
Array Integrity is checked using a predefined address sequence (proprietary), and this operation is
executed on selected and unlocked blocks. Once the operation is completed, the results of the reads can be
checked by reading the MISR value (stored in UMISR0-4), to determine if an incorrect read, or ECC
detection was noted.
The internal MISR calculator is a 32-bit register.
The 128 bit data, the 16 ECC data and the single and double ECC errors of the two Double Words are
therefore captured by the MISR through 5 different read accesses at the same location.
The whole check is done through five complete scans of the memory address space:
1. The first pass will scan only bits 31-0 of each page.
2. The second pass will scan only bits 63-32 of each page.
3. The third pass will scan only bits 95-64 of each page.
4. The fourth pass will scan only bits 127-96 of each page.
5. The fifth pass will scan only the ECC bits (8 + 8) and the single and double ECC errors (2 + 2) of
both Double Words of each page.
The 128 bit data and the 16 ECC data are sampled before the eventual ECC correction, while the single
and double error flags are sampled after the ECC evaluation.
Only data from existing and unlocked locations are captured by the MISR.
The MISR can be seeded to any value by writing the UMISR0-4 registers.
The Array Integrity Self Check consists of the following sequence of events:
1. Set UTE in UT0 by writing the related password in UT0.
2. Select the block(s) to be checked by writing ‘1’s to the appropriate register(s) in LMS or HBS
registers.
Note that Lock and Select are independent. If a block is selected and locked, no Array Integrity
Check will occur.
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor