PXD10RM Datasheet, PDF (1257/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

NOTE
After reset, NREE and NFEE are set to ‘0’, therefore the NMI functionality
is disabled after reset and must be enabled explicitly by software.
Once the pad’s NMI functionality has been enabled, the pad cannot be reconfigured in the IOMUX to
override or disable the NMI.
The NMI destination interrupt is controlled by the user through the configuration of the NDSS bits. See
Table 41-4 for details.
An NMI supports a status flag and an overrun flag which are located in the NSR register (see Table 41-3).
This register is a clear-by-write-1 register type, preventing inadvertent overwriting of other flags in the
same register. The status flag is set whenever an NMI event is detected. The overrun flag is set whenever
an NMI event is detected and the status flag is set (i.e. has not yet been cleared).
NOTE
The overrun flag is cleared by writing a ‘1’ to the appropriate overrun bit in
the NSR register. If the status bit is cleared and the overrun bit is still set, the
pending interrupt will not be cleared.
41.5.3 External Wakeups/Interrupts
The Wakeup Unit supports up to 19 external wakeup/interrupts which can be allocated to any pad
necessary at the SoC level. This allocation is fixed per SoC.
The Wakeup Unit supports three interrupt vectors to the interrupt controller of the SoC. Each interrupt
vector can support up to the number of external interrupt sources from the device pads with the total across
all vectors being equal to the number of external interrupt sources. Each external interrupt source is
assigned to exactly one interrupt vector. The interrupt vector assignment is sequential so that one interrupt
vector is for external interrupt sources 0 through N-1, the next is for N through N+M-1, and so forth.
Refer to Figure 41-13 for an overview of the external interrupt implementation for the example of three
interrupt vectors with up to eight external interrupt sources each.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
41-11