PXD10RM Datasheet, PDF (306/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

11.7.2.9 DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn)
The DSPIx_RXFRn registers provide visibility into the RX FIFO for debugging purposes. Each register is
an entry in the RX FIFO. The DSPIx_RXFR registers are read-only. Reading the DSPIx_RXFRn registers
does not alter the state of the RX FIFO. The device uses four registers to implement the RX FIFO, that is
DSPIx_RXFR0–DSPIx_RXFR3 are used.
Address:
Base + 0x007C (DSPIx_RXFR0)
Base + 0x0080 (DSPIx_RXFR1)
Base + 0x0084 (DSPIx_RXFR2)
Base + 0x0088 (DSPIx_RXFR3)
Base + 0x008C (DSPIx_RXFR4)
Access: R/O
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
RXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-10. DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn)
Table 11-17 describes the field in the DSPI receive FIFO register.
Table 11-17. DSPIx_RXFRn Field Descriptions
Field
Description
0–15 Reserved, must be cleared.
16–31 Receive data. Contains the received SPI data.
RXDATA
[15:0]
11.8 Functional Description
The DSPI supports full-duplex, synchronous serial communications between the MCU and peripheral
devices. All communications are through an SPI-like protocol.
The DSPI has one configuration:
• Serial peripheral interface (SPI) configuration in which the DSPI operates as a basic SPI or a
queued SPI.
The DCONF field in the DSPIx_MCR register determines the DSPI configuration. Refer to Table 11-3 for
the DSPI configuration values.
11-24
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor