PXD10RM Datasheet, PDF (611/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 17-44. NVLML field descriptions (continued)
Field
Description
16:31
LLK15-0: Low address space block LocK 15-0 (Read/Write)
These bits are used to lock the blocks of Low Address Space from Program and Erase.
LLK3-0 are related to sectors B1F3-0, respectively. LLK15-4 are not used for this memory cut.
A value of 1 in a bit of the LLK register signifies that the corresponding block is locked for Program and
Erase.
A value of 0 in a bit of the LLK register signifies that the corresponding block is available to receive
Program and Erase pulses.
The LLK register is not writable once an interlock write is completed until MCR.DONE is set at the
completion of the requested operation. Likewise, the LLK register is not writable if a high voltage operation
is suspended.
Upon reset, information from the Test Flash block is loaded into the LLK registers. The LLK bits may be
written as a register. Reset will cause the bits to go back to their Test Flash block value. The default value
of the LLK bits (assuming erased fuses) would be locked.
In the event that blocks are not present (due to configuration or total memory size), the LLK bits will default
to locked, and will not be writable. The reset value will always be 1 (independent of the Test Flash block),
and register writes will have no effect.
In the 80 KB Flash Macrocell bits LLK15-4 are read-only and locked at 1.
LLK is not writable unless LME is high.
0: Low Address Space Block is unlocked and can be modified (if also SLL.SLK=0).
1: Low Address Space Block is locked and cannot be modified.
17.3.6.4 High address space Block Locking register (HBL)
Address Offset: 0x0008
Reset value: 0x000000XX, initially determined by NVHBL, located in test sector.
17.3.6.5 Non-volatile High address space Block Locking register (NVHBL)
Address Offset: 0x403DF0
Delivery value: 0xFFFFFFFF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
HBE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0 HLK5 HLK4 HLK3 HLK2 HLK1 HLK0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0 rw/X rw/X rw/X rw/X rw/X rw/X
Figure 17-29. Non-volatile High address space Block Locking register (NVHBL)
The High Address Space Block Locking register provides a means to protect blocks from being modified.
The HBL register has a related non-volatile High Address Space Block Locking register located in Test
Flash that contains the default reset value for HBL: The NVHBL register is read during the reset phase of
the Flash Module and loaded into the HBL.
The NVHBL register is a 64-bit register, the 32 most significative bits of which (bits 63-32) are ‘don’t care’
and eventually used to manage ECC codes.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
17-61