PXD10RM Datasheet, PDF (431/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

set the point at which the DCU pauses fetching data from memory. The maximum size of any DMA burst
is fixed to 16 pixels and so is dependent on the graphic encoding. The lower thresholds are set by the
INP_BUF_Pm_LO bit fields.
Each of the four input FIFOs has two flags that indicate whether the FIFO has reached its upper or lower
threshold. The Pm_FIFO_HI_FLAG flags (where m is the position of the pixel in the blend stack)
indicates that the input FIFO has reached the upper threshold. The Pm_FIFO_LO_FLAG indicates that the
input FIFO has less data than its low threshold. Depending on when the low threshold is reached this may
indicate a number of scenarios
• The expected graphical data is not available for the DCU to load
• The DCU is reaching the end of a frame and does not need to load any more data
• The blend stack does not need pixels of this priority
In the situation where the data is not available to the DCU then there may or may not be an impact to the
data visible on the panel. In the situation where the output FIFO is full then it is possible for the DCU to
accept a delay before it requires to use the incoming data.
The output FIFO is not accessible to the user but it is possible to set thresholds that control the DCU
behavior when the FIFO is becoming full or empty and observe the lower threshold. This can help detect
and avert situations where the DCU is running out of data to send to the panel.
The buffer thresholds are set in the THRESHOLD register. The upper threshold is set by the
OUT_BUF_HIGH bit field and this indicates that sufficient data exists in the output buffer and processing
should stop until the DCU uses some of the values in the FIFO. If this value is set too low then the
possibility of the DCU running out of data to drive the panel is increased. The lower threshold is set by the
OUT_BUF_LOW bit field.
When the output FIFO has emptied below its low threshold (OUT_BUF_LOW bit field) it sets the
UNDRUN bit. In an under run situation there may or may not be an impact to the data visible on the panel.
The impact depends on whether the DCU is reaching the end of a frame and how close to running out the
threshold is set.
The best guide to indicate whether the DCU is able to supply the required pixel information to the panel
is the output buffer. If the output is indicating that it is running out of data then the input FIFOs may help
identify the areas of memory that are restricting the supply of data. Using these indicators can help to set
the DCU thresholds and ensure that the data throughput on the MCU is balanced correctly for all master
devices.
Finally, note that the number of DCU clock cycles to fetch and blend each pixel increases with the depth
of the blend stack. However, the time taken to process the pixel data is fixed by the timing requirements
of the panel. Therefore, for full performance across all color encodings the ratio between the DCU clock
and the pixel clock must increase as the blend stack depth increases. For two-pixel blending, the minimum
DCU clock must be twice the TFT pixel clock. For three-pixel blending, the minimum DCU clock must
be three times the TFT pixel clock. For four-pixel blending, the minimum DCU clock must be four times
the TFT pixel clock.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
12-99