PXD10RM Datasheet, PDF (559/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

The user may not read some registers (UMISR0-4, UT1-2 and part of UT0) until the Power-Down Mode
is exited. On the contrary write access is locked on all the registers in Power-Down Mode.
When enabled the flash memory module returns to its previous state in all cases unless it was in the process
of executing an erase high voltage operation at the time of entering Power-Down Mode.
If the flash memory module enters Power-Down Mode during an erase operation, the MCR[ESUS] bit is
set. The user may resume the erase operation when the module exits Power-Down Mode by clearing the
MCR[ESUS] bit. MCR[EHV] must be high to resume the erase operation.
If the flash memory module is configured to enter Power-Down Mode during a program operation, the
operation will be completed and the Power-Down Mode will be entered only after the programming ends.
If the flash memory module is put in Power-Down Mode and the Vector Table remains mapped in the Flash
Address space, the user must take care that the flash memory module will strongly increase the interrupt
response time by adding several Wait States.
It is forbidden to enter Low Power Mode when the Power-Down Mode is active.
17.2.5.3 Low Power Mode
The Low Power Mode turns off most of the DC current sources within the Flash Module.
The module (Flash Core and Registers) is not accessible for read or write after entering Low Power mode.
The wake-up time from Low Power Mode is faster than the wake-up time from Power-Down Mode.
The user may not read some registers (UMISR0-4, UT1-2 and part of UT0) until the Low Power Mode is
exited. Write access is locked on all the registers in Low Power Mode.
When exiting from Low Power Mode the flash memory module returns to its previous state in all cases
unless it was in the process of executing an erase high-voltage operation at the time of entering Low Power
Mode.
If the flash memory module enters Low Power Mode during an erase operation, the MCR[ESUS] bit is set.
The user may resume the erase operation when the module exits Low Power Mode by clearing the
MCR[ESUS] bit. The MCR[EHV] bit must be high to resume the erase operation.
If the flash memory module is configured to enter Low Power Mode during a program operation, the
operation will be completed and the Low Power Mode will be entered only after the programming ends.
It is forbidden to enter Power-Down Mode when the Low Power Mode is active.
17.2.6 Register description
The Flash User Registers mapping is shown in Table 17-6.
Table 17-6. Flash 528 KB single bank registers
Register name
Module Configuration Register (MCR)
Address
Offset
0x0000
Location
on page 11
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
17-9