PXD10RM Datasheet, PDF (259/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

EMIOSCNT[n]
0x000007
0x000006
0x000005
cycle n
cycle n+1
write to A2
match A1 write to A2
match A1
cycle n+2
match A1
0x000001
TIME
FLAG set event
FLAG pin/register
FLAG clear
A2 value
A1 value
Prescaler ratio = 1
0x000006
0x000005
0x000007
0x000005
0x000007
Figure 9-25. Modulus Counter Buffered (MCB) Up Count mode
0x000007
Figure 9-26 describes the MCB in up/down counter mode (MODE[0:6]=10101bb). A1 register is updated
at the cycle boundary. If A2 is written in cycle n, this new value will be used in cycle n+1 for A1 match.
Flags are generated only at A1 match start if MODE[5] is 0. If MODE[5] is set to 1 flags are also generated
at the cycle boundary.
EMIOSCNT[n]
0x000007
0x000006
0x000005
write to A2
cycle n
match A1
cycle n+1
match A1
write to A2
cycle n+2
0x000001
FLAG set event
TIME
FLAG pin/register
FLAG clear
A2 value
A1 value
Prescaler ratio = 1
0x000006
0x000005
0x000005
0x000007
0x000007
Figure 9-26. Modulus Counter Buffered (MCB) Up/Down Mode
Figure 9-27 describes in more detail the A1 register update process in up counter mode. The A1 load signal
is generated at the last system clock period of a counter cycle. Thus, A1 is updated with A2 value at the
same time that the counter (EMIOSCNT[n]) is loaded with 0x1. The load signal pulse has the duration of
one system clock period. If A2 is written within cycle n its value is available at A1 at the first clock of
cycle n+1 and the new value is used for match at cycle n+1. The update disable bits OU[n] of
EMIOSOUDIS register can be used to control the update of this register, thus allowing to delay the A1
register update for synchronization purposes.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-33