PXD10RM Datasheet, PDF (208/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

8.7.3 Register description
Address offset: 0x0000
Reset value: 0b00000000_00000000_00000011_00000000
0
1
2
3
4
5
6
7
8
reserved
Base Address: 0xC3FE_0080
9
10
11
12
13
14
15
LPRCTRIM
r
rw
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
LPRCDIV
reserved
S_LPR
C
reserved
r
rw
r
r
r
Figure 8-20. Low Power RC Control Register (LPRC_CTL)
Table 8-19. Low Power RC Control Register (LPRC_CTL) field descriptions
Field
Bits 0-10
Bits 11-15
Bits 16-18
Bits 19-23
Bits 24-26
Bits 27
Bits 28-31
Description
Reserved
LPRCTRIM[4:0]: Low power RC trimming bits
Note: All configurations cannot be used. Please refer to the device data sheet.
Reserved
LPRCDIV[4:0]: Low Power RC clock division factor
These bits specify the low power RC oscillator output clock division factor. The output clock is divided
by the factor LPRCDIV+1.
Reserved
S_LPRC: Low Power RC clock status
0: LPRC is not providing a stable clock.
1: LPRC is providing a stable clock.
Reserved
Note: LPRC_CTL register is writable only in supervisor mode.
8.8 FIRC digital interface
8.8.1 Introduction
The FIRC digital interface controls the main internal 16 MHz RC oscillator (FIRC). It holds control and
status registers accessible for application.
8-30
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor