PXD10RM Datasheet, PDF (1025/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 30-18. QSPI_SPISR Field Descriptions (continued)
Field
Description
TFFF
TX FIFO Fill Flag. The TFFF bit provides a method for the QuadSPI to request more entries to be
added to the TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be cleared
by host software or an acknowledgement from the DMA controller when the TX FIFO is full.
0 TX FIFO is full
1 TX FIFO is not full
RFOF
RX FIFO Overflow Flag. The RFOF bit indicates that an overflow condition in the RX FIFO has
occurred. The bit is set when the RX FIFO and shift register are full and a transfer is initiated. The bit
remains set until cleared by software.
0 RX FIFO overflow has not occurred
1 RX FIFO overflow has occurred
RFDF
RX FIFO Drain Flag. The RFDF bit provides a method for the QuadSPI to request that entries be
removed from the RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
cleared by host software or an acknowledgement from the DMA controller when the RX FIFO is
empty.
0 RX FIFO is empty
1 RX FIFO is not empty
TXCTR
TX FIFO Counter. The TXCTR field indicates the number of valid entries in the TX FIFO. The TXCTR
is incremented every time the QSPI_PUSHR is written. The TXCTR is decremented every time a SPI
Command is executed and the SPI data is transferred to the shift register.
TXNXTPTR
Transmit Next Pointer. The TXNXTPTR field indicates which TX FIFO Entry will be transmitted during
the next transfer. The TXNXTPTR field is updated every time SPI data is transferred from the TX
FIFO to the shift register. See Section 30.5.2.10.4, Transmit FIFO Underrun Interrupt Request,” for
more details.
RXCTR
RX FIFO Counter. The RXCTR field indicates the number of entries in the RX FIFO. The RXCTR is
decremented every time the QSPI_POPR is read. The RXCTR is incremented every time data is
transferred from the shift register to the RX FIFO.
POPNXTPT Pop Next Pointer. The POPNXTPTR field contains a pointer to the RX FIFO entry that will be returned
R
when the QSPI_POPR is read. The POPNXTPTR is updated when the QSPI_POPR is read. See
Section 30.5.2.6, Receive First In First Out (RX FIFO) Buffering Mechanism,” for more details.
30.4.3.6 SPI Interrupt and DMA Request Select and Enable Register
(QSPI_SPIRSER)
The QSPI_SPIRSER serves two purposes. It enables flag bits in the QSPI_SPISR to generate DMA
requests or interrupt requests. The QSPI_SPIRSER also selects the type of request to be generated. See the
individual bit descriptions for information on the types of requests the bits support. The user must not write
to the QSPI_SPIRSER while the QuadSPI is in the Running state.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-21