PXD10RM Datasheet, PDF (1183/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

length of the integration phase the ITGCNTLD setting determines the DCNT value to switch the
integration polarity for DC Offset Cancellation depending from the OFFCNC bit setting.
When the down counter reaches 0x0000 and the associated divider period has expired the appropriate flag
is set and the corresponding interrupt is triggered depending from the interrupt enable bit. Note that polling
the DCNT register for 0x0000 is misleading since the DCNT time out is reached at the end of the divider
period belonging to the value of 0x0000. Refer to Section 36.6.3, Watching Internal States of the SSD”.
Table 36-14 below shows details how the BLNDIV/ITGDIV and BLNCNTLD/ITGCNTLD settings
determine the length and granularity of the blanking and integration phase depending from the bus clock
frequency.
Table 36-14. Blanking and Integration Phase Length Vs. Bus Clock¹
Bus Clock
40 MHz
64 MHz
80 MHz
BLNDIV/ITGDIV
0
Timing Granularity 0.2 s
Max. length of BLN/ITG 13.107 ms
1 _{Numbers rounded appropriately}
7
25.6 s
1.678 s
0
0.125 s
8.192 ms
7
16 s
1.049 s
0
0.1 s
6.554 ms
7
12.8 s
0.839 s
36.4.1.4.2 Integration Accumulator
This is the fundamental sub block of the SSD, it is responsible for collecting the result of the back EMF
integration from the -modulator located in the analog block. The only time when the value of the
accumulator can change is during the integration phase of a BIS.
In terms of signal processing the ITGACC register is the counterpart of the -modulator in the analog
block, working as the -demodulator: Depending from the ACDIV bits in the PRESCALE register the
output of the analog block is sampled periodically and the content of the accumulator incremented or
decremented. Therefore the ITGACC register in fact counts the ‘imbalance’ between 1 and 0 output
samples from the analog block.
The value of the ITGACC register can change only during the integration phase of an ongoing BIS. Before
the first update the content is initialized to 0x0000 and starting from that it is incremented or decremented
according to the -modulator output.
Number format is two’s complement, if an overflow (attempt to increment ITGACC register value of
0x7FFF) or an underflow (attempt to decrement ITGACC register value of 0x8000) the ACOVIF bit
indicates the over-/underflow condition, the SSD interrupt is triggered if the ACOVIE bit is set and the
ITGACC register values is not changed. For the rest of the integration phase of the current BIS the
ITGACC register value does not change. Reaching the accumulator end values without an
over-/underflow condition does not prevent the ITGACC register from incrementing 0x8000 (-32768) or
decrementing 0x7FFF (+32767).
Table 36-15 below shows details how the ACDIV setting determines the -demodulator sampling clock
w.r.t. the bus clock. The recommended setting for the sampling is a resulting clock between 500 kHz and
2 MHz. Therefore the ACDIV values for sampling clock values in this recommended range are given:
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
36-17